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functional block diagram r b r f dac a dac a latch input latch a input latch b input latch c input latch d input latch e input latch f input latch g dac b latch dac c latch dac d latch dac e latch dac f latch dac g latch dac b dac c dac d dac e dac f dac g v b ref v d ref r g fb v g ref v f ref v e ref fb fb r e r d r c fb fb r a fb ref v a v c ref v dd dgnd ldac clr ad7568 12 12 12 12 12 12 12 12 12 12 12 12 12 12 v h ref a0 control logic + input shift register clkin sdin sdout input latch h dac h latch dac h r h fb 12 12 fsin i a i a i b i b i c i d i c i d i e i f i e i f i g i h i g i h agnd 12 out1 out2 out1 out2 out1 out2 fb out1 out2 out1 out2 out1 out2 out1 out2 out1 out2 a lc 2 mos octal 12-bit dac ad7568 features eight 12-bit dacs in one package 4-quadrant multiplication separate references single +5 v supply low power: 1 mw versatile serial interface simultaneous update capability reset function 44-pin pqfp and plcc applications process control automatic test equipment general purpose instrumentation pin configurations plastic quad flatpack plastic leaded chip carrier ad7568 top view (not to scale) 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 pin 1 identifier nc v b ref v d ref r g fb v g ref v f ref v e ref fb r f fb r e fb r d r c fb fb r b r a fb ref v a v c ref v dd dgnd ldac clr v h ref a0 clkin sdin sdout r h fb fsin i c i f i e i h agnd nc nc = no connect out2 i e out1 i d out1 i d out2 out1 i c out2 i b out1 i b out2 out1 i h out2 i a out2 i a out1 out1 i f out2 i g out1 i g out2 ad7568 pqfp top view not to scale nc = no connect nc v ref c v ref b r fb b i out1 b i out1 c nc v ref f v ref g r fb g r fb f i out2 f i out2 e i out1 e v dd dgnd agnd r fb e i out1 h i out2 h ldac fsin sdin sdout clr v ref e r fb d i out1 d a0 i out2 a i out1 a clkin v ref d v ref a r fb a i out2 b i out2 g v ref h r fb h i out1 g 4412 64 5 21 24 23 22 18 20 19 39 38 35 34 33 37 36 3 7 8 11 12 13 9 10 404142 25 28 27 26 43 31 30 29 32 15 16 17 14 top view (not to scale) ad7568 plcc i out2 d i out2 c r fb c i out1 f general description the ad7568 contains eight 12-bit dacs in one monolithic de- vice. the dacs are standard current output with separate v ref , i out1 , i out2 and r fb terminals. the ad7568 is a serial input device. data is loaded using fsin , clkin and sdin. one address pin, a0, sets up a de- vice address, and this feature may be used to simplify device loading in a multi-dac environment. all dacs can be simultaneously updated using the asynchro- nous ldac input and they can be cleared by asserting the asynchronous clr input. the ad7568 is housed in a space-saving 44-pin plastic quad flatpack and 44-lead plcc. information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. rev. c
C2C ad7568Cspecifications 1 parameter ad7568b 2 units test conditions/comments accuracy resolution 12 bits 1 lsb = v ref /2 12 = 1.22 mv when v ref = 5 v relative accuracy 0.5 lsb max differential nonlinearity 0.9 lsb max all grades guaranteed monotonic over temperature gain error +25 c 4 lsbs max t min to t max 5 lsbs max gain temperature coefficient 2 ppm fsr/ c typ 5 ppm fsr/ c max output leakage current i out1 @ +25 c 10 na max see terminology section t min to t max 200 na max reference input input resistance 5 k w min typical input resistance = 7 k w 9k w max ladder resistance mismatch 2 % max typically 0.6% digital inputs v inh , input high voltage 2.4 v min v inl , input low voltage 0.8 v max i inh , input current 1 m a max c in , input capacitance 10 pf max power requirements v dd range 4.75/5.25 v min/v max power supply sensitivity d gain/ d v dd C75 db typ i dd 300 m a max v inh = 4.0 v min, v inl = 0.4 v max 3.5 ma max v inh = 2.4 v min, v inl = 0.8 v max ac performance characteristics parameter ad7568b 2 units test conditions/comments dynamic performance output voltage settling time 500 ns typ to 0.01% of full-scale range. dac latch alternately loaded with all 0s and all 1s. digital to analog glitch impulse 40 nvCs typ measured with v ref = 0 v. dac register alternately loaded with all 0s and all 1s. multiplying feedthrough error C66 db max v ref = 20 v pk-pk, 10 khz sine wave. dac latch loaded with all 0s. output capacitance 60 pf max all 1s loaded to dac. 30 pf max all 0s loaded to dac. channel-to-channel isolation C76 db typ feedthrough from any one reference to the others with 20 v pk-pk, 10 khz sine wave applied. digital crosstalk 40 nvCs typ effect of all 0s to all 1s code transition on nonselected dacs. digital feedthrough 40 nvCs typ feedthrough to any dac output with fsin high and square wave applied to sdin and sclk. total harmonic distortion C83 db typ v ref = 6 v rms, 1 khz sine wave. output noise spectral density @ 1 khz 20 nv/ ? hz all 1s loaded to the dac. v ref = 0 v. output op amp is ad op07. notes 1 temperature range as follows: b version: C40 c to +85 c. 2 all specifications also apply for v ref = +10 v, except relative accuracy which degrades to 1 lsb. specifications subject to change without notice. (v dd = +4.75 v to +5.25 v; i out1 = i out2 = o v; v ref = +5 v; t a = t min to t max , unless otherwise noted) (these characteristics are included for design guidance and are not subject to test. dac output op amp is ad843.) rev. c
ad7568 C3C timing specifications limit at limit at parameter t a = +25 8 ct a = C40 8 c to +85 8 c units description t 1 100 100 ns min clkin cycle time t 2 40 40 ns min clkin high time t 3 40 40 ns min clkin low time t 4 30 30 ns min fsin setup time t 5 30 30 ns min data setup time t 6 5 5 ns min data hold time t 7 90 90 ns min fsin hold time t 8 2 70 70 ns max sdout valid after clkin falling edge t 9 40 40 ns min ldac , clr pulse width notes 1 sample tested at +25 c to ensure compliance. all input signals are specified with tr = tf = 5 ns (10% to 90% of 5 v) and timed from a voltage level of 1.6 v. 2 t 8 is measured with the load circuit of figure 2 and defined as the time required for the output to cross 0.8 v or 2.4 v. clkin (i) sdin (i) sdout (o) db15 db0 db15 db0 fsin (i) ldac, clr t 1 t 4 t 7 t 2 t 3 t 6 t 5 t 8 t 9 notes 1. ao is hardwired high or low. figure 1. timing diagram (v dd = +5 v 6 5%; i out1 = i out2 = 0 v; t a = t min to t max , unless otherwise noted) 1.6ma i ol +2.1v i oh 200m a c l 50pf to output pin figure 2. load circuit for digital output timing specifications rev. c
ad7568 absolute maximum ratings t a = 25c, unless otherwise noted parameter rating v dd to dgnd ?0.3 v to +6 v i out1 to dgnd ?0.3 v to v dd +0.3 v i out2 to dgnd ?0.3 v to v dd +0.3 v digital input voltage to dgnd ?0.3 v to v dd +0.3 v v rfb , v ref to dgnd 15 v input current to any pin except supplies 1 10 ma operating temperature range commercial plastic (b versions) ?40c to +85c storage temperature range ?65c to +150c lead temperature (soldering, 10 sec) 300c power dissipation (any package) to 75c 250 mw derates above 75c by 10 mw/c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution 1 transient currents of up to 100 ma will not cause scr latch-up. pin description mnemonic description v dd positive power supply. this is 5 v 5%. dgnd digital ground. agnd analog ground v refa to v refh dac reference inputs. r fba to r fbh dac feedback resistor pins. i outa to i outh dac current output terminals. agnd this pin connects to the back gates of the current steering switches. it should be connected to the signal ground of the s ystem. clkin clock input. data is clocked into the inp ut shift register on the falling edges of clkin. add a pull-down resistor on the clock line to avoid timing issues. fsin level-triggered control input (active low). this is the frame synchronization signal for the input data. when fsin goes low, it enables the input shift register, and data is transferred on the falling edges of clkin. if the address bit is valid, the 12-bi t dac data is transferred to the appropriate input latch on the sixteenth falling edge after fsin goes low. sdin serial data input. the device accepts a 16-bit word. the first bit (db15) is the dac msb, with the remaining bits following. next comes the device address bit, a0. if this does not correspo nd to the logic level on pin a0, the data is ignored. finally comes the three dac select bits. these determine which dac in the device is selected for loading. sdout this shift register output allows multiple devi ces to be connected in a daisy-chain configuration. a0 device address pin. this input gives the device an address. if db3 of the serial input stream does not correspond to this, the data that follows is ignored and not loaded to any input latch. however, it will appear at sdout irrespective of this. ldac asynchronous ldac input. when this input is taken low, all dac latche s are simultaneously updated with the contents of the input latches. clr asynchronous clr input. when this input is taken low, all dac latch outputs go to zero.
ad7568 C5C terminology relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endpoints of the dac transfer function. it is measured after adjusting for zero error and full-scale error and is normally ex- pressed in least significant bits or as a percentage or full-scale reading. differential nonlinearity differential nonlinearity is the difference between the measured change and the ideal 1 lsb change between any two adjacent codes. a specified differential nonlinearity of 1 lsb maximum ensures monotonicity. gain error gain error is a measure of the output error between an ideal dac and the actual device output. it is measured with all 1s in the dac after offset error has been adjusted out and is expressed in least significant bits. gain error is adjustable to zero with an external potentiometer. output leakage current output leakage current is current which flows in the dac lad- der switches when these are turned off. for the i out1 terminal, it can be measured by loading all 0s to the dac and measuring the i out1 current. minimum current will flow in the i out2 line when the dac is loaded with all 1s. this is a combination of the switch leakage current and the ladder termination resistor current. the i out2 leakage current is typically equal to that in i out1 . output capacitance this is the capacitance from the i out1 pin to agnd. output voltage settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. for the ad7568, it is specified with the ad843 as the output op amp. digital to analog glitch impulse this is the amount of charge injected into the analog output when the inputs change state. it is normally specified as the area of the glitch in either pa-secs or nv-secs, depending upon whether the glitch is measured as a current or voltage signal. it is measured with the reference input connected to agnd and the digital inputs toggled between all 1s and all 0s. ac feedthrough error this is the error due to capacitive feedthrough from the dac reference input to the dac i out terminal, when all 0s are loaded in the dac. channel-to-channel isolation channel-to-channel isolation refers to the proportion of input signal from one dacs reference input which appears at the output of any other dac in the device and is expressed in dbs. digital crosstalk the glitch impulse transferred to the output of one converter due to a change in digital input code to the other converter is defined as the digital crosstalk and is specified in nv-secs. digital feedthrough when the device is not selected, high frequency logic activity on the device digital inputs is capacitively coupled through the de- vice to show up as noise on the i out pin and subsequently on the op amp output. this noise is digital feedthrough. table i. ad7568 loading sequence db15 db0 db11 db10 db9 db8 db7 db6 db5 db4 db3 db2 db1 db0 a0 ds2 ds1 ds0 table ii. dac selection ds2 ds1 ds0 function 0 0 0 dac a selected 0 0 1 dac b selected 0 1 0 dac c selected 0 1 1 dac d selected 1 0 0 dac e sclected 1 0 1 dac f selected 1 1 0 dac g sclected 1 1 1 dac h selected rev. c
ad7568 C6C 5.5 0.0 5.0 1.5 0.5 1.0 1.0 0.0 3.0 2.0 2.5 3.5 4.0 4.5 5.0 4.0 3.0 2.0 digital input ?volts i ?ma dd v = +5v t = +25 c dd a figure 3. supply current vs. logic input voltage 1.0 0.0 10.0 0.3 0.1 4.0 0.2 2.0 0.6 0.4 0.5 0.7 0.8 0.9 8.0 6.0 v = +5v t = +25 c dd a v ?volts ref inl ?lsbs figure 6. integral nonlinearity error vs. v ref 10 90 100 0% 50mv 5v 200ns 200ns digital inputs ad713 output v = +5v t = +25 c v = +10v op amp = ad713 dd a ref figure 9. digital-to-analog glitch impulse Ctypical performance curves 2 0 85 ?5 ?0 1 60 10 35 temperature ? c i ?ma dd v = +5v dd v = +2.4v ih v = +4v ih figure 4. supply current vs. temperature 1.0 0.0 4095 0.6 0.2 2048 0.4 0 0.8 digital code inl spread ?lsbs v = +10v v = +5v t = +25 c ref dd a figure 7. typical dac to dac linearity matching 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 10 3 10 4 10 5 10 6 frequency ?hz v b/v c ?dbs out out v c = 20v pk-pk sine wave all other reference inputs grounded dac c loaded with all 1s all other dacs loaded with all 0s ref figure 10. channel-to-channel isolation (1 dac to 1 dac) 1.0 0.0 10.0 0.3 0.1 4.0 0.2 2.0 0.6 0.4 0.5 0.7 0.8 0.9 8.0 6.0 v = +5v t = +25 c dd a v ?volts ref dnl ?lsbs figure 5. differential nonlinearity error vs. v ref ?0 ?00 ?5 ?5 ?0 ?0 ?0 ?5 ?5 ?0 ?5 10 2 10 3 10 4 10 5 frequency ?hz thd ?dbs v = +5v t = +25 c v = 6v rms op amp = ad713 dd a in figure 8. total harmonic distortion vs. frequency 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 10 3 10 4 10 5 10 6 frequency ?hz v b/v c ?dbs out out v b grounded all other reference inputs = 20v pk-pk sine wave dac b loaded with all 0s all other dacs loaded with all 1s ref figure 11. channel-to-channel isolation (1 dac to all other dacs) rev. c
ad7568 C7C interface section the ad7568 is a serial input device. three lines control the se- rial interface, fsin , clkin and sdin. the timing diagram is shown in figure 1. when the fsin input goes low, data appearing on the sdin line is clocked into the input shift register on each falling edge of clkin. when sixteen bits have been received, the register loading is automatically disabled until the next falling edge of fsin detected. also, the received data is clocked out on the next rising edge of clkin and appears on the sdout pin. this feature allows several devices to be connected together in a daisy chain fashion. when the sixteen bits have been received in the input shift regis- ter, db3 (a0) is checked to see if it corresponds to the state of pin a0. if it does, then the word is accepted. otherwise, it is dis- regarded. this allows the user to address one of two ad7568s in a very simple fashion. db0 to db2 of the 16-bit word deter- mine which of the eight dac input latches is to be loaded. when the ldac line goes low, all eight dac latches in the de- vice are simultaneously loaded with the contents of their respec- tive input latches, and the outputs change accordingly. bringing the clr line low resets the dac latches to all 0s. the input latches are not affected, so that the user can revert to the previous analog output if desired. 16-bit input shift register clkin sdin sdout fsin figure 14. input logic 0 ?00 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 ?0 10 3 10 4 10 5 10 6 10 7 v = +5v t = +25 c v = 20v pk-pk op amp = ad713 dd a in dac loaded with all 1s dac loaded with all 0s figure 12. multiplying frequency response vs. digital code general description d/a section the ad7568 contains eight 12-bit current-output d/a convert- ers. a simplified circuit diagram for one of the d/a converters is shown in figure 13. a segmented scheme is used whereby the 2 msbs of the 12-bit data word are decoded to drive the three switches a, b and c. the remaining 10 bits of the data word drive the switches s0 to s9 in a standard rC2r ladder configuration. each of the switches a to c steers 1/4 of the total reference cur- rent with the remaining current passing through the rC2r section. each dac in the device has separate v ref , i out1 , i out2 and r fb pins. this makes the device extremely versatile and allows dacs in the same device to be configured differently. when an output amplifier is connected in the standard configu- ration of figure 15, the output voltage is given by: v out = Cd ? v ref where d is the fractional representation of the digital word loaded to the dac. thus, in the ad7568, d can be set from 0 to 4095/4096. v ref 2r 2r 2r 2r 2r 2r 2r cba s9 s8 s9 r fb i out1 i out2 r r r r/2 shown for all 1s on dac figure 13. simplified d/a circuit diagram rev. c
ad7568 C8C unipolar binary operation (2-quadrant multiplication) figure 15 shows the standard unipolar binary connection dia- gram for one of the dacs in the ad7568. when v in is an ac signal, the circuit performs 2-quadrant multiplication. resistors r1 and r2 allow the user to adjust the dac gain error. offset can be removed by adjusting the output amplifier offset voltage. a1 should be chosen to suit the application. for example, the ad op07 or op177 are ideal for very low bandwidth applica- tions while the ad843 and ad845 offer very fast settling time in wide bandwidth applications. appropriate multiple versions of these amplifiers can be used with the ad7568 to reduce board space requirements. the code table for figure 15 is shown in table iii. dac a a1 i a out1 i a out2 ad7568 v out r a fb v a ref v in notes 1. only one dac is shown for clarity. 2. digital input connections are omitted. 3. c1 phase compensation (5?5pf) may be required when using high speed amplifier, a1. r2 10w r1 20w signal gnd a1: op-177 adop-07 ad711 ad843 ad845 c1 figure 15. unipolar binary operation table iii. unipolar binary code table digital input analog output msblsb (v out as shown in figure 15) 1111 1111 1111 Cv ref (4095/4096) 1000 0000 0001 Cv ref (2049/4096) 1000 0000 0000 Cv ref (2048/4096) 0111 1111 1111 Cv ref (2047/4096) 0000 0000 0001 Cv ref (1/4096) 0000 0000 0000 Cv ref (0/4096) = 0 note nominal lsb size for the circuit of figure 15 is given by: v ref (1/4096). bipolar operation (4-quadrant multiplication) figure 16 shows the standard connection diagram for bipolar operation of any one of the dacs in the ad7568. the coding is offset binary as shown in table iv. when v in is an ac signal, the circuit performs 4-quadrant multiplication. to maintain the gain error specifications, resistors r3, r4 and r5 should be ra- tio matched to 0.01%. dac a a1 i a out1 i a out2 ad7568 v out r a fb v a ref v in notes 1. only one dac is shown for clarity. 2. digital input connections are omitted. 3. c1 phase compensation (5?5pf) may be required when using high speed amplifier, a1. r2 10w r1 20w signal gnd c1 a2 r3 10kw r5 20kw 20kw r4 figure 16. bipolar operation (4-quadrant multiplication) table iv. bipolar (offset binary) code table digital input analog output msb . . . . . lsb (v out as shown in figure 16) 1111 1111 1111 +v ref (2047/2048) 1000 0000 0001 +v ref (1/2048) 1000 0000 0000 +v ref (0/2048) = 0 0111 1111 1111 Cv ref (1/2048) 0000 0000 0001 Cv ref (2047/2048) 0000 0000 0000 Cv ref (2048/2048) = Cv ref note nominal lsb size for the circuit of figure 16 is given by: v ref (1/2048). single supply circuits the ad7568 operates from a single +5 v supply, and this makes it ideal for single supply systems. when operating in such a system, it is not possible to use the standard circuits of figures 15 and 16 since these invert the analog input, v in . there are two alternatives. one of these continues to operate the dac as a current-mode device, while the other uses the voltage switch- ing mode. dac a a1 i a out1 i a out2 ad7568 v bias v out r a fb v a ref v in notes 1. only one dac is shown for clarity. 2. digital input connections are omitted. 3. c1 phase compensation (5?5pf) may be required when using high speed amplifier, a1. figure 17. single supply current-mode operation rev. c
ad7568 C9C current mode circuit in the current mode circuit of figure 17, i out2 , and hence i out1 , is biased positive by an amount v bias . for the circuit to operate correctly, the dac ladder termination resistor must be connected internally to i out2 . this is the case with the ad7568. the output voltage is given by: v out = d r fb r dac v bias - v in () {} + v bias as d varies from 0 to 4095/4096, the output voltage varies from v out = v bias to v out = 2 v bias C v in . v bias should be a low impedance source capable of sinking and sourcing all possible variations in current at the i out2 terminal without any problems. voltage mode circuit figure 18 shows dac a of the ad7568 operating in the voltage-switching mode. the reference voltage, v in is applied to the i out1 pin, i out2 is connected to agnd and the output volt- age is available at the v ref terminal. in this configuration, a positive reference voltage results in a positive output voltage making single supply operation possible. the output from the dac is a voltage at a constant impedance (the dac ladder re- sistance). thus, an op amp is necessary to buffer the output voltage. the reference voltage input no longer sees a constant input impedance, but one which varies with code. so, the volt- age input should be driven from a low impedance source. it is important to note that v in is limited to low voltages be- cause the switches in the dac no longer have the same source- drain voltage. as a result, their on-resistance differs and this degrades the integral linearity of the dac. also, v in must not go negative by more than 0.3 volts or an internal diode will turn on, causing possible damage to the device. this means that the full-range multiplying capability of the dac is lost. dac a a1 i a out1 i a out2 ad7568 v out r a fb v a ref v in notes 1) only one dac is shown for clarity. 2) digital input connections are omitted. 3) c1 phase compensation (5?5pf) may be required when using high speed amplifier, a1. r1 r2 figure 18. single supply voltage switching mode operation applications programmable state variable filter the ad7568 with its multiplying capability and fast settling time is ideal for many types of signal conditioning applications. the circuit of figure 19 shows its use in a state variable filter design. this type of filter has three outputs: low pass, high pass and bandpass. the particular version shown in figure 19 uses one half of an ad7568 to control the critical parameters f 0 , q and a 0 . instead of several fixed resistors, the circuit uses the dac equivalent resistances as circuit elements. thus, r1 in figure 19 is controlled by the 12-bit digital word loaded to dac a of the ad7568. this is also the case with r2, r3 and r4. the fixed resistor r5 is the feedback resistor, r fb b. dac equivalent resistance, r eq = (r ladder 3 4096)/n where: r ladder is the dac ladder resistance. n is the dac digital code in decimal (0 < n < 4096). dac a (r1) dac b (r2) 1/2 x ad7568 a1 a1 r8 30k w high pass output dac c (r3) i a out1 i c out1 r b fb v b ref v in i b out1 v c ref dac d (r4) c3 10pf c1 1000pf r7 30k w c1 1000pf low pass output band pass output v a ref i c out2 i b out2 i a out2 i d out2 v d ref i d out1 a2 a3 r6 10kw notes 1. a1, a2, a3, a4: 1/4 x ad713 2. digital input connections are omitted. 3. c3 is a compensation capacitor to eliminate q and gain variations caused by amplifier gain bandwidth limitations. figure 19. programmable 2nd order state variable filter rev. c
ad7568 C10C in the circuit of figure 19: c1 = c2, r7 = r8, r3 = r4 (i.e., the same code is loaded to each dac). resonant frequency, f 0 = 1/(2p r3c1). quality factor, q = (r6/r8)?(r2/r5). bandpass gain, a0 = Cr2/r1. using the values shown in figure 19, the q range is 0.3 to 5, and the f 0 range is 0 to 12 khz. application hints output offset cmos d/a converters in circuits such as figures 15, 16 and 17 exhibit a code dependent output resistance which in turn can cause a code dependent error voltage at the output of the ampli- fier. the maximum amplitude of this error, which adds to the d/a converter nonlinearity, depends on v os , where v os is the amplifier input offset voltage. for the ad7568 to maintain specified accuracy with v ref at 10 v, it is recommended that v os be no greater than 500 m v, or (50 3 10 C6 )?(v ref ), over the temperature range of operation. suitable amplifiers include the ad op07, ad op27, op177, ad711, ad845 or multiple ver- sions of these. temperature coefficients the gain temperature coefficient of the ad7568 has a maxi- mum value of 5 ppm/ c and a typical value of 2 ppm/ c. this corresponds to gain shifts of 2 lsbs and 0.8 lsbs respectively over a 100 c temperature range. when trim resistors r1 and r2 are used to adjust full-scale in figures 15 and 16, their tem- perature coefficients should be taken into account. for further information see gain error and gain temperature coefficient of cmos multiplying dacs, application note, publication number e630cC5C3/86, available from analog devices. high frequency considerations the output capacitances of the ad7568 dacs work in con- junction with the amplifier feedback resistance to add a pole to the open loop response. this can cause ringing or oscillation. stability can be restored by adding a phase compensation ca- pacitor in parallel with the feedback resistor. this is shown as c1 in figures 15, 16 and 17. microprocessor interfacing ad7568C80c51 interface a serial interface between the ad7568 and the 80c51 micro- controller is shown in figure 20. txd of the 80c51 drives sclk of the ad7568 while rxd drives the serial data line of the part. the fsin signal is derived from the port line p3.3. the 80c51 provides the lsb of its sbuf register as the first bit in the serial data stream. therefore, the user will have to ensure that the data in the sbuf register is arranged correctly so that the data word transmitted to the ad7568 corresponds to the loading sequence shown in table i. when data is to be trans- mitted to the part, p3.3 is taken low. data on rxd is valid on the falling edge of txd. the 80c51 transmits its serial data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. to load data to the ad7568, p3.3 is left low af- ter the first eight bits are transferred, and a second byte of data is then transferred serially to the ad7568. when the second se- rial transfer is complete, the p3.3 line is taken high. note that the 80c51 outputs the serial data byte in a format which has the lsb first. the ad7568 expects the msb first. the 80c51 transmit routine should take this into account. p3.5 p3.4 p3.3 txd rxd sclk sdin clr ldac fsin 80c51* ad7568* *additional pins omitted for clarity figure 20. ad7568 to 80c51 interface ldac and clr on the ad7568 are also controlled by 80c51 port outputs. the user can bring ldac low after every two bytes have been transmitted to update the dac which has been programmed. alternatively, it is possible to wait until all the in- put registers have been loaded (sixteen byte transmits) and then update the dac outputs. ad7568C68hc11 interface figure 21 shows a serial interface between the ad7568 and the 68hc11 microcontroller. sck of the 68hc11 drives sclk of the ad7568, while the mosi output drives the serial data line of the ad7568. the fsin signal is derived from a port line (pc7 shown). for correct operation of this interface, the 68hc11 should be configured such that its cpol bit is a 0 and its cpha bit is a 1. when data is to be transmitted to the part, pc7 is taken low. when the 68hc11 is configured like this, data on mosi is valid on the falling edge of sck. the 68hc11 transmits its serial data in 8-bit bytes (msb first), with only eight falling clock edges occurring in the transmit cycle. to load data to the ad7568, pc7 is left low after the first eight bits are transferred, and a second byte of data is then transferred serially to the ad7568. when the second serial transfer is complete, the pc7 line is taken high. rev. c
ad7568 C11C pc5 pc6 pc7 sck mosi clkin sdin clr ldac fsin 68hc11* ad7568* *additional pins omitted for clarity figure 21. ad7568 to 68hc11 interface in figure 21, ldac and clr are controlled by the pc6 and pc5 port outputs. as with the 80c51, each dac of the ad7568 can be updated after each two-byte transfer, or else all dacs can be simultaneously updated. ad7568Cadsp-2101 interface figure 22 shows a serial interface between the ad7568 and the adsp-2101 digital signal processor. the adsp-2101 may be set up to operate in the sport transmit normal internal framing mode. the following adsp-2101 conditions are rec- ommended: internal sclk; active high framing signal; 16-bit word length. transmission is initiated by writing a word to the tx register after the sport has been enabled. the data is then clocked out on every rising edge of sclk after tfs goes low. tfs stays low until the next data transfer. fo tfs dt sclk clkin sdin clr ldac fsin adsp-2101* ad7568* *additional pins omitted for clarity +5v figure 22. ad7568 to adsp-2101 interface ad7568Ctms320c25 interface figure 23 shows an interface circuit for the tms320c25 digital signal processor. the data on the dx pin is clocked out of the processors transmit shift register by the clkx signal. sixteen-bit transmit format should be chosen by setting the fo bit in the st1 register to 0. the transmit operation be- gins when data is written into the data transmit register of the tms320c25. this data will be transmitted when the fsx line goes low while clkx is high or going high. the data, starting xf fsx dx clkx clkin sdin clr ldac fsin tms320c25* ad7568* *additional pins omitted for clarity +5v clock generation figure 23. ad7568 to tms320c25 interface with the msb, is then shifted out to the dx pin on the rising edge of clkx. when all bits have been transmitted, the user can update the dac outputs by bringing the xf output flag low. multiple dac systems if there are only two ad7568s in a system, there is a simple way of programming each. this is shown in figure 24. if the user wishes to program one of the dacs in the first ad7568, then db3 of the serial bit stream should be set to 0, to correspond to the state of the a0 pin on that device. if the user wishes to pro- gram a dac in the second ad7568, then db3 should be set to 1, to correspond to a0 on that device. fo tfs dt sclk clkin sdin clr ldac fsin adsp-2101* ad7568* *additional pins omitted for clarity +5v a0 clkin sdin clr ldac fsin ad7568* +5v a0 figure 24. interfacing adsp-2101 to two ad7568s rev. c
ad7568 C12C for systems which contain larger numbers of ad7568s and where the user also wishes to read back the dac contents for diagnostic purposes, the sdout pin may be used to daisy chain several devices together and provide the necessary serial readback. an example with the 68hc11 is shown in figure 25. the routine below shows how four ad7568s would be pro- grammed in such a system. data is transmitted at the mosi pin of the 68hc11. it flows through the input shift registers of the ad7568s and finally appears at the sdout pin of dac n. so, the readback routine can be invoked any time after the first four words have been transmitted (the four input shift registers in the chain will now be filled up and further activity on the clkin pin will result in data being read back to the microcomputer through the miso pin). system connectivity can be verified in this manner. for a four-device system (32 dacs) a two-line to four-line decoder is necessary. note that to program the 32 dacs, 35 transmit operations are needed. in the routine, three words must be retransmitted. the first word for dacs #3, #2 and #1 must be transmitted twice in order to synchronize their arrival at the sdin pin with a0 going low. table v. routine for loading 4 ad7568s connected as in figure 25 bring pc7 ( fsin ) low to allow writing to the ad7568s. enable ad7568 #4 (bring a0 low). disable the others. transmit 1st 16-bit word: data for dac h, #4 . . . . . . . . transmit 9th 16-bit word: data for dac h, #3 transmit 9th 16-bit word again: data for dac h, #3 transmit 10th 16-bit word: data for dac g, #3 transmit 11th 16-bit word: data for dac f, #3 enable ad7568 #3, disable the others. transmit 12th 16-bit word: data for dac e, #3 . . . . . . . . transmit 17th 16-bit word: data for dac h, #2 transmit 17th 16-bit word again: data for dac h, #2 transmit 18th 16-bit word: data for dac g, #2 enable ad7568 #2, disable the others. transmit 19th 16-bit word: data for dac f, #2 . . . . . . . . transmit 25th word: data for dac h, #1 enable ad7568 #1, disable the others. transmit 25th word again: data for dac h, #1 transmit 26th word: data for dac g, #1 . . . . . . . . transmit 32nd word: data for dac a, #1 bring pc7 ( fsin ) high to disable writing to the ad7568s. pc7 sck pc6 miso sclk sdin ldac fsin 68hc11* ad7568* (dac 1) *additional pins omitted for clarity a0 sclk ldac fsin ad7568* (dac 2) a0 decode logic sdin mosi sdout sdout sclk ldac fsin ad7568* (dac n) a0 sdin sdout figure 25. multi-dac system rev. c
ad7568 outline dimensions compliant to jedec standards mo-047-ac controlling dimensions are in inches; millimeter dimensions (in parentheses) are rounded-off inch equivalents for reference only and are not appropriate for use in design. bottom view (pins up) 6 7 40 39 17 18 29 28 top view (pins down) 0.656 (16.66) 0.650 (16.51) sq 0.048 (1.22) 0.042 (1.07) 0.050 (1.27) bsc 0.695 (17.65) 0.685 (17.40) sq 0.048 (1.22) 0.042 (1.07) 0.021 (0.53) 0.013 (0.33) 0.630 (16.00) 0.590 (14.99) 0.032 (0.81) 0.026 (0.66) 0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07) 0.020 (0.51) min 0.120 (3.05) 0.090 (2.29) 0.045 (1.14) 0.025 (0.64) r pin 1 identifier figure 26. 44-lead plastic leaded chip carrier [plcc] (p-44) dimensions shown in inches and (millimeters) compliant to jedec standards mo-112-aa-1 041807-a 14.15 13.90 sq 13.65 0.45 0.30 2.45 max 1.03 0.88 0.73 top view (pins down) 12 44 1 22 23 34 33 11 0.25 min 2.20 2.00 1.80 7 0 view a rotated 90 ccw 0.23 0.11 10.20 10.00 sq 9.80 0.80 bsc lead pitch lead width 0.10 coplanarity v i e w a s e a t i n g p l a n e 1 . 9 5 r e f pin 1 figure 27. 44-lead metric quad flat package [mqfp] (s-44-2) dimensions shown in millimeters ordering guide model 1 temperature range linearity error (lsb s) package description package option ad7568bp ?40c to +85c 0.5 44-lead plastic leaded chip carrier [plcc] p-44 ad7568bp-reel ?40c to +85c 0.5 44-lead plastic leaded chip carrier [plcc] p-44 ad7568bpz ?40c to +85c 0.5 44-lead plastic leaded chip carrier [plcc] p-44 AD7568BPZ-REEL ?40c to +85c 0.5 44-lead plastic leaded chip carrier [plcc] p-44 ad7568bsz ?40c to +85c 0.5 44-lead metric quad flat package [mqfp] s-44-2 ad7568bsz-reel ?40c to +85c 0.5 44-lead metric quad flat package [mqfp] s-44-2 1 z = rohs compliant part
ad7568 revision history 2/12rev. b to rev. c changes to clr description, pin description table ................... 4 updated outline dimensions ........................................................ 13 changes to ordering guide ........................................................... 13 added revision history section ................................................... 14 ?2011 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d10541-0-2/12(c)

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